module counter_tb; 
  reg clk, reset, enable; 
  wire [3:0] count; 
    
  counter U0 ( 
  .clk    (clk), 
  .reset  (reset), 
  .enable (enable), 
  .count  (count) 
  ); 
    
  initial begin
    clk = 0; 
    reset = 0; 
    enable = 0; 
  end 
    
  always  
    #5 clk = !clk; 
    
  initial  begin
    $dumpfile ("output/counter.vcd"); 
    $dumpvars; 
  end 
    
  initial  begin
    $display("\t\ttime,\tclk,\treset,\tenable,\tcount"); 
    $monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,reset,enable,count); 
  end 
    
  initial 
  #100 $finish; 
    
  reg [3:0] count_compare; 

  always @ (posedge clk) 
  if (reset == 1'b1) begin
    count_compare <= 0; 
  end else if ( enable == 1'b1) begin
    count_compare <= count_compare + 1; 
  end

  always @ (posedge clk) 
  if (count_compare != count) begin 
    $display ("DUT Error at time %d", $time); 
    $display (" Expected value %d, Got Value %d", count_compare, count); 
    #5 -> terminate_sim; 
  end 

  event terminate_sim;  
  initial begin  
  @ (terminate_sim); 
    #5 $finish; 
  end
    
endmodule
